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Apply patch provided in issue #224. Add support for ARM64.

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This commit is contained in:
Ignacio 2015-07-20 23:47:01 +02:00
parent 4ef408b591
commit 58617584d4
4 changed files with 14 additions and 3 deletions
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7
extern/poshlib/posh.h vendored
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@ -493,6 +493,11 @@ LLVM:
# define POSH_CPU_STRING "ARM"
#endif
#if defined __aarch64__
# define POSH_CPU_AARCH64 1
# define POSH_CPU_STRING "ARM64"
#endif
#if defined mips || defined __mips__ || defined __MIPS__ || defined _MIPS
# define POSH_CPU_MIPS 1
# if defined _R5900
@ -666,7 +671,7 @@ LLVM:
** the MIPS series, so we have to be careful about those.
** ----------------------------------------------------------------------------
*/
#if defined POSH_CPU_X86 || defined POSH_CPU_AXP || defined POSH_CPU_STRONGARM || defined POSH_OS_WIN32 || defined POSH_OS_WINCE || defined __MIPSEL__
#if defined POSH_CPU_X86 || defined POSH_CPU_AXP || defined POSH_CPU_STRONGARM || defined POSH_CPU_AARCH64 || defined POSH_OS_WIN32 || defined POSH_OS_WINCE || defined __MIPSEL__
# define POSH_ENDIAN_STRING "little"
# define POSH_LITTLE_ENDIAN 1
#else

3
src/nvcore/Debug.cpp
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@ -656,6 +656,9 @@ namespace
# elif NV_CPU_PPC
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext.regs->nip;
# elif NV_CPU_AARCH64
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext.pc;
# else
# error "Unknown CPU"
# endif

3
src/nvcore/nvcore.h
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@ -93,6 +93,7 @@
// NV_CPU_X86_64
// NV_CPU_PPC
// NV_CPU_ARM
// NV_CPU_AARCH64
#define NV_CPU_STRING POSH_CPU_STRING
@ -105,6 +106,8 @@
# define NV_CPU_PPC 1
#elif defined POSH_CPU_STRONGARM
# define NV_CPU_ARM 1
#elif defined POSH_CPU_AARCH64
# define NV_CPU_AARCH64 1
#else
# error "Unsupported CPU"
#endif

4
src/nvthread/Atomic.h
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@ -58,7 +58,7 @@ namespace nv {
uint32 ret = *ptr; // on x86, loads are Acquire
nvCompilerReadBarrier();
return ret;
#elif POSH_CPU_STRONGARM
#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
// need more specific cpu type for armv7?
// also utilizes a full barrier
// currently treating laod like x86 - this could be wrong
@ -82,7 +82,7 @@ namespace nv {
nvCompilerWriteBarrier();
*ptr = value; // on x86, stores are Release
//nvCompilerWriteBarrier(); // @@ IC: Where does this barrier go? In nvtt it was after, in Witness before. Not sure which one is right.
#elif POSH_CPU_STRONGARM
#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
// this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier();
*ptr = value; //strex?