From be5a3050819208cdab2e7742925871c81f2caf92 Mon Sep 17 00:00:00 2001 From: "C.W. Betts" Date: Sun, 23 Aug 2020 18:03:02 -0600 Subject: [PATCH] Update Half.cpp Replace old(?) usage of NV_CC_GCC with NV_CC_GNUC --- src/nvmath/Half.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/nvmath/Half.cpp b/src/nvmath/Half.cpp index c4ea48f..d5a5426 100644 --- a/src/nvmath/Half.cpp +++ b/src/nvmath/Half.cpp @@ -294,7 +294,7 @@ uint32 _uint32_nlz( uint32 x ) { // Count Leading Zeros static inline uint32 _uint32_cntlz( uint32 x ) { -#if NV_CC_GCC +#if NV_CC_GNUC /* On PowerPC, this will map to insn: cntlzw */ /* On Pentium, this will map to insn: clz */ uint32 is_x_nez_msb = _uint32_neg( x ); @@ -692,7 +692,7 @@ __asm /* This method is faster than the OpenEXR implementation (very often * used, eg. in Ogre), with the additional benefit of rounding, inspired - * by James Tursa’s half-precision code. */ + * by James TursaÂ’s half-precision code. */ static inline uint16_t float_to_half_branch(uint32_t x) { uint16_t bits = (x >> 16) & 0x8000; /* Get the sign */ @@ -742,7 +742,7 @@ static inline uint16_t float_to_half_branch(uint32_t x) #define S256(x) S64((x)), S64((x)+64), S64((x)+128), S64((x)+192) #define S1024(x) S256((x)), S256((x)+256), S256((x)+512), S256((x)+768) -/* Lookup table-based algorithm from “Fast Half Float Conversions” +/* Lookup table-based algorithm from “Fast Half Float Conversions” * by Jeroen van der Zijp, November 2008. No rounding is performed, * and some NaN values may be incorrectly converted to Inf. */ static inline uint16_t float_to_half_nobranch(uint32_t x)