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@ -48,7 +48,6 @@ namespace nv {
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nvDebugCheck((intptr_t(ptr) & 3) == 0);
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#if POSH_CPU_X86 || POSH_CPU_X86_64
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nvCompilerReadBarrier();
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uint32 ret = *ptr; // on x86, loads are Acquire
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nvCompilerReadBarrier();
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return ret;
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@ -73,7 +72,6 @@ namespace nv {
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nvDebugCheck((intptr_t(&value) & 3) == 0);
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#if POSH_CPU_X86 || POSH_CPU_X86_64
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nvCompilerWriteBarrier();
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*ptr = value; // on x86, stores are Release
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nvCompilerWriteBarrier();
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#elif POSH_CPU_STRONGARM
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@ -87,6 +85,27 @@ namespace nv {
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}
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template <typename T>
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inline void storeReleasePointer(volatile T * pTo, T from)
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{
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NV_COMPILER_CHECK(sizeof(T) == sizeof(intptr_t));
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nvDebugCheck((((intptr_t)pTo) % sizeof(intptr_t)) == 0);
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nvDebugCheck((((intptr_t)&from) % sizeof(intptr_t)) == 0);
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nvCompilerWriteBarrier();
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*pTo = from; // on x86, stores are Release
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}
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template <typename T>
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inline T loadAcquirePointer(volatile T * ptr)
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{
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NV_COMPILER_CHECK(sizeof(T) == sizeof(intptr_t));
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nvDebugCheck((((intptr_t)ptr) % sizeof(intptr_t)) == 0);
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T ret = *ptr; // on x86, loads are Acquire
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nvCompilerReadBarrier();
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return ret;
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}
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// Atomics. @@ Assuming sequential memory order?
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#if NV_CC_MSVC
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