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564 lines
25 KiB
C++
564 lines
25 KiB
C++
// Branch-free implementation of half-precision (16 bit) floating point
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// Copyright 2006 Mike Acton <macton@gmail.com>
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE
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//
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// Half-precision floating point format
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// ------------------------------------
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//
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// | Field | Last | First | Note
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// |----------|------|-------|----------
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// | Sign | 15 | 15 |
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// | Exponent | 14 | 10 | Bias = 15
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// | Mantissa | 9 | 0 |
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//
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// Compiling
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// ---------
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//
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// Preferred compile flags for GCC:
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// -O3 -fstrict-aliasing -std=c99 -pedantic -Wall -Wstrict-aliasing
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//
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// This file is a C99 source file, intended to be compiled with a C99
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// compliant compiler. However, for the moment it remains combatible
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// with C++98. Therefore if you are using a compiler that poorly implements
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// C standards (e.g. MSVC), it may be compiled as C++. This is not
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// guaranteed for future versions.
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//
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// Features
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// --------
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//
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// * QNaN + <x> = QNaN
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// * <x> + +INF = +INF
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// * <x> - -INF = -INF
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// * INF - INF = SNaN
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// * Denormalized values
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// * Difference of ZEROs is always +ZERO
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// * Sum round with guard + round + sticky bit (grs)
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// * And of course... no branching
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//
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// Precision of Sum
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// ----------------
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//
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// (SUM) uint16 z = half_add( x, y );
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// (DIFFERENCE) uint16 z = half_add( x, -y );
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//
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// Will have exactly (0 ulps difference) the same result as:
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// (For 32 bit IEEE 784 floating point and same rounding mode)
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//
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// union FLOAT_32
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// {
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// float f32;
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// uint32 u32;
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// };
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//
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// union FLOAT_32 fx = { .u32 = half_to_float( x ) };
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// union FLOAT_32 fy = { .u32 = half_to_float( y ) };
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// union FLOAT_32 fz = { .f32 = fx.f32 + fy.f32 };
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// uint16 z = float_to_half( fz );
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//
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#include "half.h"
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#include <stdio.h>
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// Load immediate
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static inline uint32 _uint32_li( uint32 a )
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{
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return (a);
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}
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// Decrement
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static inline uint32 _uint32_dec( uint32 a )
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{
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return (a - 1);
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}
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// Complement
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static inline uint32 _uint32_not( uint32 a )
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{
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return (~a);
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}
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// Negate
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static inline uint32 _uint32_neg( uint32 a )
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{
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#if NV_CC_MSVC
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// prevent msvc warning.
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return ~a + 1;
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#else
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return (-a);
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#endif
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}
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// Extend sign
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static inline uint32 _uint32_ext( uint32 a )
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{
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return (((int32)a)>>31);
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}
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// And
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static inline uint32 _uint32_and( uint32 a, uint32 b )
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{
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return (a & b);
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}
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// And with Complement
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static inline uint32 _uint32_andc( uint32 a, uint32 b )
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{
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return (a & ~b);
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}
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// Or
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static inline uint32 _uint32_or( uint32 a, uint32 b )
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{
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return (a | b);
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}
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// Shift Right Logical
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static inline uint32 _uint32_srl( uint32 a, int sa )
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{
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return (a >> sa);
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}
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// Shift Left Logical
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static inline uint32 _uint32_sll( uint32 a, int sa )
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{
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return (a << sa);
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}
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// Add
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static inline uint32 _uint32_add( uint32 a, uint32 b )
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{
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return (a + b);
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}
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// Subtract
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static inline uint32 _uint32_sub( uint32 a, uint32 b )
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{
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return (a - b);
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}
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// Select on Sign bit
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static inline uint32 _uint32_sels( uint32 test, uint32 a, uint32 b )
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{
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const uint32 mask = _uint32_ext( test );
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const uint32 sel_a = _uint32_and( a, mask );
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const uint32 sel_b = _uint32_andc( b, mask );
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const uint32 result = _uint32_or( sel_a, sel_b );
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return (result);
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}
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// Load Immediate
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static inline uint16 _uint16_li( uint16 a )
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{
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return (a);
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}
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// Extend sign
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static inline uint16 _uint16_ext( uint16 a )
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{
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return (((int16)a)>>15);
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}
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// Negate
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static inline uint16 _uint16_neg( uint16 a )
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{
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return (-a);
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}
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// Complement
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static inline uint16 _uint16_not( uint16 a )
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{
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return (~a);
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}
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// Decrement
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static inline uint16 _uint16_dec( uint16 a )
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{
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return (a - 1);
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}
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// Shift Left Logical
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static inline uint16 _uint16_sll( uint16 a, int sa )
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{
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return (a << sa);
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}
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// Shift Right Logical
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static inline uint16 _uint16_srl( uint16 a, int sa )
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{
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return (a >> sa);
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}
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// Add
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static inline uint16 _uint16_add( uint16 a, uint16 b )
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{
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return (a + b);
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}
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// Subtract
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static inline uint16 _uint16_sub( uint16 a, uint16 b )
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{
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return (a - b);
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}
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// And
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static inline uint16 _uint16_and( uint16 a, uint16 b )
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{
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return (a & b);
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}
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// Or
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static inline uint16 _uint16_or( uint16 a, uint16 b )
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{
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return (a | b);
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}
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// Exclusive Or
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static inline uint16 _uint16_xor( uint16 a, uint16 b )
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{
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return (a ^ b);
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}
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// And with Complement
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static inline uint16 _uint16_andc( uint16 a, uint16 b )
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{
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return (a & ~b);
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}
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// And then Shift Right Logical
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static inline uint16 _uint16_andsrl( uint16 a, uint16 b, int sa )
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{
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return ((a & b) >> sa);
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}
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// Shift Right Logical then Mask
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static inline uint16 _uint16_srlm( uint16 a, int sa, uint16 mask )
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{
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return ((a >> sa) & mask);
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}
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// Add then Mask
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static inline uint16 _uint16_addm( uint16 a, uint16 b, uint16 mask )
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{
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return ((a + b) & mask);
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}
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// Select on Sign bit
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static inline uint16 _uint16_sels( uint16 test, uint16 a, uint16 b )
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{
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const uint16 mask = _uint16_ext( test );
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const uint16 sel_a = _uint16_and( a, mask );
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const uint16 sel_b = _uint16_andc( b, mask );
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const uint16 result = _uint16_or( sel_a, sel_b );
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return (result);
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}
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// Count Leading Zeros
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static inline uint32 _uint32_cntlz( uint32 x )
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{
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#ifdef __GNUC__
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/* On PowerPC, this will map to insn: cntlzw */
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/* On Pentium, this will map to insn: clz */
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uint32 nlz = __builtin_clz( x );
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return (nlz);
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#else
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const uint32 x0 = _uint32_srl( x, 1 );
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const uint32 x1 = _uint32_or( x, x0 );
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const uint32 x2 = _uint32_srl( x1, 2 );
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const uint32 x3 = _uint32_or( x1, x2 );
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const uint32 x4 = _uint32_srl( x3, 4 );
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const uint32 x5 = _uint32_or( x3, x4 );
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const uint32 x6 = _uint32_srl( x5, 8 );
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const uint32 x7 = _uint32_or( x5, x6 );
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const uint32 x8 = _uint32_srl( x7, 16 );
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const uint32 x9 = _uint32_or( x7, x8 );
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const uint32 xA = _uint32_not( x9 );
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const uint32 xB = _uint32_srl( xA, 1 );
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const uint32 xC = _uint32_and( xB, 0x55555555 );
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const uint32 xD = _uint32_sub( xA, xC );
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const uint32 xE = _uint32_and( xD, 0x33333333 );
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const uint32 xF = _uint32_srl( xD, 2 );
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const uint32 x10 = _uint32_and( xF, 0x33333333 );
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const uint32 x11 = _uint32_add( xE, x10 );
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const uint32 x12 = _uint32_srl( x11, 4 );
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const uint32 x13 = _uint32_add( x11, x12 );
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const uint32 x14 = _uint32_and( x13, 0x0f0f0f0f );
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const uint32 x15 = _uint32_srl( x14, 8 );
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const uint32 x16 = _uint32_add( x14, x15 );
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const uint32 x17 = _uint32_srl( x16, 16 );
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const uint32 x18 = _uint32_add( x16, x17 );
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const uint32 x19 = _uint32_and( x18, 0x0000003f );
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return ( x19 );
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#endif
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}
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// Count Leading Zeros
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static inline uint16 _uint16_cntlz( uint16 x )
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{
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#ifdef __GNUC__
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/* On PowerPC, this will map to insn: cntlzw */
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/* On Pentium, this will map to insn: clz */
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uint32 x32 = _uint32_sll( x, 16 );
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uint16 nlz = (uint16)__builtin_clz( x32 );
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return (nlz);
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#else
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const uint16 x0 = _uint16_srl( x, 1 );
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const uint16 x1 = _uint16_or( x, x0 );
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const uint16 x2 = _uint16_srl( x1, 2 );
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const uint16 x3 = _uint16_or( x1, x2 );
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const uint16 x4 = _uint16_srl( x3, 4 );
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const uint16 x5 = _uint16_or( x3, x4 );
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const uint16 x6 = _uint16_srl( x5, 8 );
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const uint16 x7 = _uint16_or( x5, x6 );
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const uint16 x8 = _uint16_not( x7 );
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const uint16 x9 = _uint16_srlm( x8, 1, 0x5555 );
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const uint16 xA = _uint16_sub( x8, x9 );
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const uint16 xB = _uint16_and( xA, 0x3333 );
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const uint16 xC = _uint16_srlm( xA, 2, 0x3333 );
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const uint16 xD = _uint16_add( xB, xC );
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const uint16 xE = _uint16_srl( xD, 4 );
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const uint16 xF = _uint16_addm( xD, xE, 0x0f0f );
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const uint16 x10 = _uint16_srl( xF, 8 );
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const uint16 x11 = _uint16_addm( xF, x10, 0x001f );
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return ( x11 );
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#endif
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}
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uint16
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half_from_float( uint32 f )
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{
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const uint32 one = _uint32_li( 0x00000001 );
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const uint32 f_e_mask = _uint32_li( 0x7f800000 );
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const uint32 f_m_mask = _uint32_li( 0x007fffff );
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const uint32 f_s_mask = _uint32_li( 0x80000000 );
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const uint32 h_e_mask = _uint32_li( 0x00007c00 );
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const uint32 f_e_pos = _uint32_li( 0x00000017 );
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const uint32 f_m_round_bit = _uint32_li( 0x00001000 );
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const uint32 h_nan_em_min = _uint32_li( 0x00007c01 );
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const uint32 f_h_s_pos_offset = _uint32_li( 0x00000010 );
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const uint32 f_m_hidden_bit = _uint32_li( 0x00800000 );
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const uint32 f_h_m_pos_offset = _uint32_li( 0x0000000d );
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const uint32 f_h_bias_offset = _uint32_li( 0x38000000 );
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const uint32 f_m_snan_mask = _uint32_li( 0x003fffff );
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const uint16 h_snan_mask = _uint32_li( 0x00007e00 );
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const uint32 f_e = _uint32_and( f, f_e_mask );
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const uint32 f_m = _uint32_and( f, f_m_mask );
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const uint32 f_s = _uint32_and( f, f_s_mask );
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const uint32 f_e_h_bias = _uint32_sub( f_e, f_h_bias_offset );
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const uint32 f_e_h_bias_amount = _uint32_srl( f_e_h_bias, f_e_pos );
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const uint32 f_m_round_mask = _uint32_and( f_m, f_m_round_bit );
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const uint32 f_m_round_offset = _uint32_sll( f_m_round_mask, one );
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const uint32 f_m_rounded = _uint32_add( f_m, f_m_round_offset );
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const uint32 f_m_rounded_overflow = _uint32_and( f_m_rounded, f_m_hidden_bit );
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const uint32 f_m_denorm_sa = _uint32_sub( one, f_e_h_bias_amount );
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const uint32 f_m_with_hidden = _uint32_or( f_m_rounded, f_m_hidden_bit );
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const uint32 f_m_denorm = _uint32_srl( f_m_with_hidden, f_m_denorm_sa );
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const uint32 f_em_norm_packed = _uint32_or( f_e_h_bias, f_m_rounded );
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const uint32 f_e_overflow = _uint32_add( f_e_h_bias, f_m_hidden_bit );
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const uint32 h_s = _uint32_srl( f_s, f_h_s_pos_offset );
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const uint32 h_m_nan = _uint32_srl( f_m, f_h_m_pos_offset );
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const uint32 h_m_denorm = _uint32_srl( f_m_denorm, f_h_m_pos_offset );
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const uint32 h_em_norm = _uint32_srl( f_em_norm_packed, f_h_m_pos_offset );
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const uint32 h_em_overflow = _uint32_srl( f_e_overflow, f_h_m_pos_offset );
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const uint32 is_e_eqz_msb = _uint32_dec( f_e );
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const uint32 is_m_nez_msb = _uint32_neg( f_m );
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const uint32 is_h_m_nan_nez_msb = _uint32_neg( h_m_nan );
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const uint32 is_e_nflagged_msb = _uint32_sub( f_e, f_e_mask );
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const uint32 is_ninf_msb = _uint32_or( is_e_nflagged_msb, is_m_nez_msb );
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const uint32 is_underflow_msb = _uint32_sub( is_e_eqz_msb, f_h_bias_offset );
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const uint32 is_nan_nunderflow_msb = _uint32_or( is_h_m_nan_nez_msb, is_e_nflagged_msb );
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const uint32 is_m_snan_msb = _uint32_sub( f_m_snan_mask, f_m );
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const uint32 is_snan_msb = _uint32_andc( is_m_snan_msb, is_e_nflagged_msb );
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const uint32 is_overflow_msb = _uint32_neg( f_m_rounded_overflow );
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const uint32 h_nan_underflow_result = _uint32_sels( is_nan_nunderflow_msb, h_em_norm, h_nan_em_min );
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const uint32 h_inf_result = _uint32_sels( is_ninf_msb, h_nan_underflow_result, h_e_mask );
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const uint32 h_underflow_result = _uint32_sels( is_underflow_msb, h_m_denorm, h_inf_result );
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const uint32 h_overflow_result = _uint32_sels( is_overflow_msb, h_em_overflow, h_underflow_result );
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const uint32 h_em_result = _uint32_sels( is_snan_msb, h_snan_mask, h_overflow_result );
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const uint32 h_result = _uint32_or( h_em_result, h_s );
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return (h_result);
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}
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uint32
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half_to_float( uint16 h )
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{
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const uint32 h_e_mask = _uint32_li( 0x00007c00 );
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const uint32 h_m_mask = _uint32_li( 0x000003ff );
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const uint32 h_s_mask = _uint32_li( 0x00008000 );
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const uint32 h_f_s_pos_offset = _uint32_li( 0x00000010 );
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const uint32 h_f_e_pos_offset = _uint32_li( 0x0000000d );
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const uint32 h_f_bias_offset = _uint32_li( 0x0001c000 );
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const uint32 f_e_mask = _uint32_li( 0x7f800000 );
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const uint32 f_m_mask = _uint32_li( 0x007fffff );
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const uint32 h_f_e_denorm_bias = _uint32_li( 0x0000007e );
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const uint32 h_f_m_denorm_sa_bias = _uint32_li( 0x00000008 );
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const uint32 f_e_pos = _uint32_li( 0x00000017 );
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const uint32 h_e_mask_minus_one = _uint32_li( 0x00007bff );
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const uint32 h_e = _uint32_and( h, h_e_mask );
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const uint32 h_m = _uint32_and( h, h_m_mask );
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const uint32 h_s = _uint32_and( h, h_s_mask );
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const uint32 h_e_f_bias = _uint32_add( h_e, h_f_bias_offset );
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const uint32 h_m_nlz = _uint32_cntlz( h_m );
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const uint32 f_s = _uint32_sll( h_s, h_f_s_pos_offset );
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const uint32 f_e = _uint32_sll( h_e_f_bias, h_f_e_pos_offset );
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const uint32 f_m = _uint32_sll( h_m, h_f_e_pos_offset );
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const uint32 f_em = _uint32_or( f_e, f_m );
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const uint32 h_f_m_sa = _uint32_sub( h_m_nlz, h_f_m_denorm_sa_bias );
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const uint32 f_e_denorm_unpacked = _uint32_sub( h_f_e_denorm_bias, h_f_m_sa );
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const uint32 h_f_m = _uint32_sll( h_m, h_f_m_sa );
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const uint32 f_m_denorm = _uint32_and( h_f_m, f_m_mask );
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const uint32 f_e_denorm = _uint32_sll( f_e_denorm_unpacked, f_e_pos );
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const uint32 f_em_denorm = _uint32_or( f_e_denorm, f_m_denorm );
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const uint32 f_em_nan = _uint32_or( f_e_mask, f_m );
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const uint32 is_e_eqz_msb = _uint32_dec( h_e );
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const uint32 is_m_nez_msb = _uint32_neg( h_m );
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const uint32 is_e_flagged_msb = _uint32_sub( h_e_mask_minus_one, h_e );
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const uint32 is_zero_msb = _uint32_andc( is_e_eqz_msb, is_m_nez_msb );
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const uint32 is_inf_msb = _uint32_andc( is_e_flagged_msb, is_m_nez_msb );
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const uint32 is_denorm_msb = _uint32_and( is_m_nez_msb, is_e_eqz_msb );
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const uint32 is_nan_msb = _uint32_and( is_e_flagged_msb, is_m_nez_msb );
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const uint32 is_zero = _uint32_ext( is_zero_msb );
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const uint32 f_zero_result = _uint32_andc( f_em, is_zero );
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const uint32 f_denorm_result = _uint32_sels( is_denorm_msb, f_em_denorm, f_zero_result );
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const uint32 f_inf_result = _uint32_sels( is_inf_msb, f_e_mask, f_denorm_result );
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const uint32 f_nan_result = _uint32_sels( is_nan_msb, f_em_nan, f_inf_result );
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const uint32 f_result = _uint32_or( f_s, f_nan_result );
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return (f_result);
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}
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uint16
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half_add( uint16 x, uint16 y )
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{
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const uint16 one = _uint16_li( 0x0001 );
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const uint16 msb_to_lsb_sa = _uint16_li( 0x000f );
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const uint16 h_s_mask = _uint16_li( 0x8000 );
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const uint16 h_e_mask = _uint16_li( 0x7c00 );
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const uint16 h_m_mask = _uint16_li( 0x03ff );
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const uint16 h_m_msb_mask = _uint16_li( 0x2000 );
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const uint16 h_m_msb_sa = _uint16_li( 0x000d );
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const uint16 h_m_hidden = _uint16_li( 0x0400 );
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const uint16 h_e_pos = _uint16_li( 0x000a );
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const uint16 h_e_bias_minus_one = _uint16_li( 0x000e );
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const uint16 h_m_grs_carry = _uint16_li( 0x4000 );
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const uint16 h_m_grs_carry_pos = _uint16_li( 0x000e );
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const uint16 h_grs_size = _uint16_li( 0x0003 );
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const uint16 h_snan = _uint16_li( 0xfe00 );
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const uint16 h_e_mask_minus_one = _uint16_li( 0x7bff );
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const uint16 h_grs_round_carry = _uint16_sll( one, h_grs_size );
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const uint16 h_grs_round_mask = _uint16_sub( h_grs_round_carry, one );
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const uint16 x_e = _uint16_and( x, h_e_mask );
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const uint16 y_e = _uint16_and( y, h_e_mask );
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const uint16 is_y_e_larger_msb = _uint16_sub( x_e, y_e );
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const uint16 a = _uint16_sels( is_y_e_larger_msb, y, x);
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const uint16 a_s = _uint16_and( a, h_s_mask );
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const uint16 a_e = _uint16_and( a, h_e_mask );
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const uint16 a_m_no_hidden_bit = _uint16_and( a, h_m_mask );
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const uint16 a_em_no_hidden_bit = _uint16_or( a_e, a_m_no_hidden_bit );
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|
const uint16 b = _uint16_sels( is_y_e_larger_msb, x, y);
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const uint16 b_s = _uint16_and( b, h_s_mask );
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|
const uint16 b_e = _uint16_and( b, h_e_mask );
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const uint16 b_m_no_hidden_bit = _uint16_and( b, h_m_mask );
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|
const uint16 b_em_no_hidden_bit = _uint16_or( b_e, b_m_no_hidden_bit );
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|
const uint16 is_diff_sign_msb = _uint16_xor( a_s, b_s );
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|
const uint16 is_a_inf_msb = _uint16_sub( h_e_mask_minus_one, a_em_no_hidden_bit );
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|
const uint16 is_b_inf_msb = _uint16_sub( h_e_mask_minus_one, b_em_no_hidden_bit );
|
|
const uint16 is_undenorm_msb = _uint16_dec( a_e );
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|
const uint16 is_undenorm = _uint16_ext( is_undenorm_msb );
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|
const uint16 is_both_inf_msb = _uint16_and( is_a_inf_msb, is_b_inf_msb );
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|
const uint16 is_invalid_inf_op_msb = _uint16_and( is_both_inf_msb, b_s );
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|
const uint16 is_a_e_nez_msb = _uint16_neg( a_e );
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|
const uint16 is_b_e_nez_msb = _uint16_neg( b_e );
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|
const uint16 is_a_e_nez = _uint16_ext( is_a_e_nez_msb );
|
|
const uint16 is_b_e_nez = _uint16_ext( is_b_e_nez_msb );
|
|
const uint16 a_m_hidden_bit = _uint16_and( is_a_e_nez, h_m_hidden );
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|
const uint16 b_m_hidden_bit = _uint16_and( is_b_e_nez, h_m_hidden );
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|
const uint16 a_m_no_grs = _uint16_or( a_m_no_hidden_bit, a_m_hidden_bit );
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|
const uint16 b_m_no_grs = _uint16_or( b_m_no_hidden_bit, b_m_hidden_bit );
|
|
const uint16 diff_e = _uint16_sub( a_e, b_e );
|
|
const uint16 a_e_unbias = _uint16_sub( a_e, h_e_bias_minus_one );
|
|
const uint16 a_m = _uint16_sll( a_m_no_grs, h_grs_size );
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|
const uint16 a_e_biased = _uint16_srl( a_e, h_e_pos );
|
|
const uint16 m_sa_unbias = _uint16_srl( a_e_unbias, h_e_pos );
|
|
const uint16 m_sa_default = _uint16_srl( diff_e, h_e_pos );
|
|
const uint16 m_sa_unbias_mask = _uint16_andc( is_a_e_nez_msb, is_b_e_nez_msb );
|
|
const uint16 m_sa = _uint16_sels( m_sa_unbias_mask, m_sa_unbias, m_sa_default );
|
|
const uint16 b_m_no_sticky = _uint16_sll( b_m_no_grs, h_grs_size );
|
|
const uint16 sh_m = _uint16_srl( b_m_no_sticky, m_sa );
|
|
const uint16 sticky_overflow = _uint16_sll( one, m_sa );
|
|
const uint16 sticky_mask = _uint16_dec( sticky_overflow );
|
|
const uint16 sticky_collect = _uint16_and( b_m_no_sticky, sticky_mask );
|
|
const uint16 is_sticky_set_msb = _uint16_neg( sticky_collect );
|
|
const uint16 sticky = _uint16_srl( is_sticky_set_msb, msb_to_lsb_sa);
|
|
const uint16 b_m = _uint16_or( sh_m, sticky );
|
|
const uint16 is_c_m_ab_pos_msb = _uint16_sub( b_m, a_m );
|
|
const uint16 c_inf = _uint16_or( a_s, h_e_mask );
|
|
const uint16 c_m_sum = _uint16_add( a_m, b_m );
|
|
const uint16 c_m_diff_ab = _uint16_sub( a_m, b_m );
|
|
const uint16 c_m_diff_ba = _uint16_sub( b_m, a_m );
|
|
const uint16 c_m_smag_diff = _uint16_sels( is_c_m_ab_pos_msb, c_m_diff_ab, c_m_diff_ba );
|
|
const uint16 c_s_diff = _uint16_sels( is_c_m_ab_pos_msb, a_s, b_s );
|
|
const uint16 c_s = _uint16_sels( is_diff_sign_msb, c_s_diff, a_s );
|
|
const uint16 c_m_smag_diff_nlz = _uint16_cntlz( c_m_smag_diff );
|
|
const uint16 diff_norm_sa = _uint16_sub( c_m_smag_diff_nlz, one );
|
|
const uint16 is_diff_denorm_msb = _uint16_sub( a_e_biased, diff_norm_sa );
|
|
const uint16 is_diff_denorm = _uint16_ext( is_diff_denorm_msb );
|
|
const uint16 is_a_or_b_norm_msb = _uint16_neg( a_e_biased );
|
|
const uint16 diff_denorm_sa = _uint16_dec( a_e_biased );
|
|
const uint16 c_m_diff_denorm = _uint16_sll( c_m_smag_diff, diff_denorm_sa );
|
|
const uint16 c_m_diff_norm = _uint16_sll( c_m_smag_diff, diff_norm_sa );
|
|
const uint16 c_e_diff_norm = _uint16_sub( a_e_biased, diff_norm_sa );
|
|
const uint16 c_m_diff_ab_norm = _uint16_sels( is_diff_denorm_msb, c_m_diff_denorm, c_m_diff_norm );
|
|
const uint16 c_e_diff_ab_norm = _uint16_andc( c_e_diff_norm, is_diff_denorm );
|
|
const uint16 c_m_diff = _uint16_sels( is_a_or_b_norm_msb, c_m_diff_ab_norm, c_m_smag_diff );
|
|
const uint16 c_e_diff = _uint16_sels( is_a_or_b_norm_msb, c_e_diff_ab_norm, a_e_biased );
|
|
const uint16 is_diff_eqz_msb = _uint16_dec( c_m_diff );
|
|
const uint16 is_diff_exactly_zero_msb = _uint16_and( is_diff_sign_msb, is_diff_eqz_msb );
|
|
const uint16 is_diff_exactly_zero = _uint16_ext( is_diff_exactly_zero_msb );
|
|
const uint16 c_m_added = _uint16_sels( is_diff_sign_msb, c_m_diff, c_m_sum );
|
|
const uint16 c_e_added = _uint16_sels( is_diff_sign_msb, c_e_diff, a_e_biased );
|
|
const uint16 c_m_carry = _uint16_and( c_m_added, h_m_grs_carry );
|
|
const uint16 is_c_m_carry_msb = _uint16_neg( c_m_carry );
|
|
const uint16 c_e_hidden_offset = _uint16_andsrl( c_m_added, h_m_grs_carry, h_m_grs_carry_pos );
|
|
const uint16 c_m_sub_hidden = _uint16_srl( c_m_added, one );
|
|
const uint16 c_m_no_hidden = _uint16_sels( is_c_m_carry_msb, c_m_sub_hidden, c_m_added );
|
|
const uint16 c_e_no_hidden = _uint16_add( c_e_added, c_e_hidden_offset );
|
|
const uint16 c_m_no_hidden_msb = _uint16_and( c_m_no_hidden, h_m_msb_mask );
|
|
const uint16 undenorm_m_msb_odd = _uint16_srl( c_m_no_hidden_msb, h_m_msb_sa );
|
|
const uint16 undenorm_fix_e = _uint16_and( is_undenorm, undenorm_m_msb_odd );
|
|
const uint16 c_e_fixed = _uint16_add( c_e_no_hidden, undenorm_fix_e );
|
|
const uint16 c_m_round_amount = _uint16_and( c_m_no_hidden, h_grs_round_mask );
|
|
const uint16 c_m_rounded = _uint16_add( c_m_no_hidden, c_m_round_amount );
|
|
const uint16 c_m_round_overflow = _uint16_andsrl( c_m_rounded, h_m_grs_carry, h_m_grs_carry_pos );
|
|
const uint16 c_e_rounded = _uint16_add( c_e_fixed, c_m_round_overflow );
|
|
const uint16 c_m_no_grs = _uint16_srlm( c_m_rounded, h_grs_size, h_m_mask );
|
|
const uint16 c_e = _uint16_sll( c_e_rounded, h_e_pos );
|
|
const uint16 c_em = _uint16_or( c_e, c_m_no_grs );
|
|
const uint16 c_normal = _uint16_or( c_s, c_em );
|
|
const uint16 c_inf_result = _uint16_sels( is_a_inf_msb, c_inf, c_normal );
|
|
const uint16 c_zero_result = _uint16_andc( c_inf_result, is_diff_exactly_zero );
|
|
const uint16 c_result = _uint16_sels( is_invalid_inf_op_msb, h_snan, c_zero_result );
|
|
|
|
return (c_result);
|
|
}
|