Apply patch provided in issue #224. Add support for ARM64.

src/nvcore/Debug.cpp

@@ -656,6 +656,9 @@ namespace
 #  elif NV_CPU_PPC
         ucontext_t * ucp = (ucontext_t *)secret;
         return (void *) ucp->uc_mcontext.regs->nip;
+#    elif NV_CPU_AARCH64
+        ucontext_t * ucp = (ucontext_t *)secret;
+        return (void *) ucp->uc_mcontext.pc;
 #    else
 #      error "Unknown CPU"
 #    endif

src/nvcore/nvcore.h

@@ -93,6 +93,7 @@
 // NV_CPU_X86_64
 // NV_CPU_PPC
 // NV_CPU_ARM
+// NV_CPU_AARCH64
 
 #define NV_CPU_STRING   POSH_CPU_STRING
 
@@ -105,6 +106,8 @@
 #   define NV_CPU_PPC 1
 #elif defined POSH_CPU_STRONGARM
 #   define NV_CPU_ARM 1
+#elif defined POSH_CPU_AARCH64
+#   define NV_CPU_AARCH64 1
 #else
 #   error "Unsupported CPU"
 #endif

src/nvthread/Atomic.h

@@ -58,7 +58,7 @@ namespace nv {
         uint32 ret = *ptr;  // on x86, loads are Acquire
         nvCompilerReadBarrier();
         return ret;
-#elif POSH_CPU_STRONGARM 
+#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
         // need more specific cpu type for armv7?
         // also utilizes a full barrier
         // currently treating laod like x86 - this could be wrong
@@ -82,7 +82,7 @@ namespace nv {
         nvCompilerWriteBarrier();
         *ptr = value;   // on x86, stores are Release
         //nvCompilerWriteBarrier(); // @@ IC: Where does this barrier go? In nvtt it was after, in Witness before. Not sure which one is right.
-#elif POSH_CPU_STRONGARM
+#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
         // this is the easiest but slowest way to do this
         nvCompilerReadWriteBarrier();
 		*ptr = value; //strex?