Fix tabs.

import/raw
castano 12 years ago
parent 56d73f05de
commit 77c2958c91

@ -85,25 +85,25 @@ namespace nv {
} }
template <typename T> template <typename T>
inline void storeReleasePointer(volatile T * pTo, T from) inline void storeReleasePointer(volatile T * pTo, T from)
{ {
NV_COMPILER_CHECK(sizeof(T) == sizeof(intptr_t)); NV_COMPILER_CHECK(sizeof(T) == sizeof(intptr_t));
nvDebugCheck((((intptr_t)pTo) % sizeof(intptr_t)) == 0); nvDebugCheck((((intptr_t)pTo) % sizeof(intptr_t)) == 0);
nvDebugCheck((((intptr_t)&from) % sizeof(intptr_t)) == 0); nvDebugCheck((((intptr_t)&from) % sizeof(intptr_t)) == 0);
nvCompilerWriteBarrier(); nvCompilerWriteBarrier();
*pTo = from; // on x86, stores are Release *pTo = from; // on x86, stores are Release
} }
template <typename T> template <typename T>
inline T loadAcquirePointer(volatile T * ptr) inline T loadAcquirePointer(volatile T * ptr)
{ {
NV_COMPILER_CHECK(sizeof(T) == sizeof(intptr_t)); NV_COMPILER_CHECK(sizeof(T) == sizeof(intptr_t));
nvDebugCheck((((intptr_t)ptr) % sizeof(intptr_t)) == 0); nvDebugCheck((((intptr_t)ptr) % sizeof(intptr_t)) == 0);
T ret = *ptr; // on x86, loads are Acquire T ret = *ptr; // on x86, loads are Acquire
nvCompilerReadBarrier(); nvCompilerReadBarrier();
return ret; return ret;
} }
// Atomics. @@ Assuming sequential memory order? // Atomics. @@ Assuming sequential memory order?

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