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E2K: added initial support for MCST Elbrus 2000

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pull/303/head
r-a-sattarov 5 years ago
parent 261948f076
commit 809c6df193
3 changed files with 1716 additions and 1691 deletions
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113
src/nvcore/Debug.cpp
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@ -30,10 +30,10 @@
#endif
#if NV_OS_XBOX
# include <Xtl.h>
# ifdef _DEBUG
# include <xbdm.h>
# endif //_DEBUG
# include <Xtl.h>
# ifdef _DEBUG
# include <xbdm.h>
# endif //_DEBUG
#endif //NV_OS_XBOX
#if !NV_OS_WIN32 && defined(HAVE_SIGNAL_H)
@ -594,83 +594,90 @@ namespace
static void * callerAddress(void * secret)
{
#if NV_OS_DARWIN
# if defined(_STRUCT_MCONTEXT)
# if NV_CPU_PPC
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__srr0;
# elif NV_CPU_X86_64
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__rip;
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__eip;
# elif NV_CPU_ARM
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__pc;
# else
# error "Unknown CPU"
# endif
# else
# if NV_CPU_PPC
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->ss.srr0;
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->ss.eip;
# else
# error "Unknown CPU"
# endif
# endif
# if defined(_STRUCT_MCONTEXT)
# if NV_CPU_PPC
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__srr0;
# elif NV_CPU_X86_64
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__rip;
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__eip;
# elif NV_CPU_ARM
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->__ss.__pc;
# else
# error "Unknown CPU"
# endif
# else
# if NV_CPU_PPC
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->ss.srr0;
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext->ss.eip;
# else
# error "Unknown CPU"
# endif
# endif
#elif NV_OS_FREEBSD
# if NV_CPU_X86_64
# if NV_CPU_X86_64
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->uc_mcontext.mc_rip;
# elif NV_CPU_X86
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->uc_mcontext.mc_eip;
# else
# error "Unknown CPU"
# endif
# else
# error "Unknown CPU"
# endif
#elif NV_OS_NETBSD
# if NV_CPU_X86_64
# if NV_CPU_X86_64
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->uc_mcontext.__gregs[_REG_RIP];
# elif NV_CPU_X86
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->uc_mcontext.__gregs[_REG_EIP];
# elif NV_CPU_PPC
# elif NV_CPU_PPC
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext.__gregs[_REG_PC];
# else
# error "Unknown CPU"
# endif
# else
# error "Unknown CPU"
# endif
#elif NV_OS_OPENBSD
# if NV_CPU_X86_64
# if NV_CPU_X86_64
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->sc_rip;
# elif NV_CPU_X86
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->sc_eip;
# else
# else
# error "Unknown CPU"
# endif
# endif
#else
# if NV_CPU_X86_64
# if NV_CPU_X86_64
// #define REG_RIP REG_INDEX(rip) // seems to be 16
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->uc_mcontext.gregs[REG_RIP];
# elif NV_CPU_X86
# elif NV_CPU_X86
ucontext_t * ucp = (ucontext_t *)secret;
return (void *)ucp->uc_mcontext.gregs[14/*REG_EIP*/];
# elif NV_CPU_PPC
# elif NV_CPU_PPC
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext.regs->nip;
# elif NV_CPU_AARCH64
# elif NV_CPU_AARCH64
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext.pc;
# else
# error "Unknown CPU"
# endif
# elif NV_CPU_E2K /* MCST Elbrus 2000 */
// e2k has 3 stacks - Procedure Stack (PS), Procedure Chain Stack (PCS) and User Stack (US)
// CR0 and CR1 (Chain Register) are the 128-bit registers of the Procedure Chain Stack (PCS)
// CR's divided into _HI and _LO 64-bit parts (as in x86, for example, AX is divided into AH and AL)
// CR0_HI stores an Instruction Pointer
ucontext_t * ucp = (ucontext_t *)secret;
return (void *) ucp->uc_mcontext.cr0_hi;
# else
# error "Unknown CPU"
# endif
#endif
// How to obtain the instruction pointers in different platforms, from mlton's source code.

9
src/nvcore/nvcore.h
Unescape Escape View File

@ -56,7 +56,7 @@
# define NV_OS_MINGW 1
# define NV_OS_WIN32 1
#elif defined POSH_OS_OSX
# define NV_OS_OSX 1 // IC: Adding this, because iOS defines NV_OS_DARWIN too.
# define NV_OS_OSX 1 // IC: Adding this, because iOS defines NV_OS_DARWIN too.
# define NV_OS_DARWIN 1
# define NV_OS_UNIX 1
#elif defined POSH_OS_IOS
@ -98,6 +98,7 @@
// NV_CPU_PPC
// NV_CPU_ARM
// NV_CPU_ARM_64
// NV_CPU_E2K /* MCST Elbrus 2000 */
#define NV_CPU_STRING POSH_CPU_STRING
@ -112,6 +113,8 @@
# define NV_CPU_ARM 1
#elif defined POSH_CPU_AARCH64
# define NV_CPU_ARM_64 1
#elif defined POSH_CPU_E2K
# define NV_CPU_E2K 1
#else
# error "Unsupported CPU"
#endif
@ -124,7 +127,7 @@
#if defined POSH_COMPILER_CLANG
# define NV_CC_CLANG 1
# define NV_CC_GNUC 1 // Clang is compatible with GCC.
# define NV_CC_GNUC 1 // Clang is compatible with GCC.
# define NV_CC_STRING "clang"
#elif defined POSH_COMPILER_GCC
# define NV_CC_GNUC 1
@ -278,7 +281,7 @@ typedef uint32 uint;
#else
#define nvStaticCheck(x) typedef char NV_STRING_JOIN2(__static_assert_,__LINE__)[(x)]
#endif
#define NV_COMPILER_CHECK(x) nvStaticCheck(x) // I like this name best.
#define NV_COMPILER_CHECK(x) nvStaticCheck(x) // I like this name best.
// Make sure type definitions are fine.
NV_COMPILER_CHECK(sizeof(int8) == 1);

37
src/nvthread/Atomic.h
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@ -55,17 +55,17 @@ namespace nv {
nvDebugCheck((intptr_t(ptr) & 3) == 0);
#if POSH_CPU_X86 || POSH_CPU_X86_64
uint32 ret = *ptr; // on x86, loads are Acquire
uint32 ret = *ptr; // on x86, loads are Acquire
nvCompilerReadBarrier();
return ret;
#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
// need more specific cpu type for armv7?
// also utilizes a full barrier
// currently treating laod like x86 - this could be wrong
// currently treating load like x86 - this could be wrong
// this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier();
uint32 ret = *ptr; // replace with ldrex?
uint32 ret = *ptr; // replace with ldrex?
nvCompilerReadWriteBarrier();
return ret;
#elif POSH_CPU_PPC64
@ -75,7 +75,17 @@ namespace nv {
// this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier();
uint32 ret = *ptr; // replace with ldrex?
uint32 ret = *ptr; // replace with ldrex?
nvCompilerReadWriteBarrier();
return ret;
#elif POSH_CPU_E2K
// need more specific cpu type for e2k?
// also utilizes a full barrier
// currently treating load like x86 - this could be wrong
// this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier();
uint32 ret = *ptr; // replace with ldrex?
nvCompilerReadWriteBarrier();
return ret;
#else
@ -90,18 +100,23 @@ namespace nv {
#if POSH_CPU_X86 || POSH_CPU_X86_64
nvCompilerWriteBarrier();
*ptr = value; // on x86, stores are Release
*ptr = value; // on x86, stores are Release
//nvCompilerWriteBarrier(); // @@ IC: Where does this barrier go? In nvtt it was after, in Witness before. Not sure which one is right.
#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
// this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier();
*ptr = value; //strex?
nvCompilerReadWriteBarrier();
*ptr = value; //strex?
nvCompilerReadWriteBarrier();
#elif POSH_CPU_PPC64
// this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier();
*ptr = value; //strex?
nvCompilerReadWriteBarrier();
*ptr = value; //strex?
nvCompilerReadWriteBarrier();
#elif POSH_CPU_E2K
// this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier();
*ptr = value; //strex?
nvCompilerReadWriteBarrier();
#else
#error "Atomics not implemented."
#endif
@ -120,7 +135,7 @@ namespace nv {
nvDebugCheck((((intptr_t)pTo) % sizeof(intptr_t)) == 0);
nvDebugCheck((((intptr_t)&from) % sizeof(intptr_t)) == 0);
nvCompilerWriteBarrier();
*pTo = from; // on x86, stores are Release
*pTo = from; // on x86, stores are Release
}
template <typename T>
@ -128,7 +143,7 @@ namespace nv {
{
NV_COMPILER_CHECK(sizeof(T) == sizeof(intptr_t));
nvDebugCheck((((intptr_t)ptr) % sizeof(intptr_t)) == 0);
T ret = *ptr; // on x86, loads are Acquire
T ret = *ptr; // on x86, loads are Acquire
nvCompilerReadBarrier();
return ret;
}

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